We design custom Clock and Power distribution circuitry which includes complete IR drop and Electromigration. We have the expertise to take behavioral RTL to GDSII, through Synthesis, Place and Route, Timing and Noise analysis, IR, Antenna, etc. We have in-house tools, flows and methodologies to assist us in providing you with the best quality and faster time-to-market.

We design, develop and analyze customizable I/O rings that include I/Os for all standards (PCI Express, HT, DDR3, PCIX, GPIO LVTTL/LVCMOS, etc.) as well as ESD protection circuitry. When analyzing such circuits we provide the package modeling for either wire-bond or flip-chip. We also provide efficient solutions when there is a need to transition from wire-bond to flip-chip or vice versa for performance or cost reduction with limited changes on the die.

We develop SERDES with integrated Clock Recovery and Clock Generation capability, A/D and D/A converters, PLLs, Voltage Regulators, etc. Among successful projects developed in the past: 8-bit pipeline A/D converters with 150MSPS, 10-bit 100MSPS pipeline ADC, 2.4GHz PLL for Wireless LAN, 802.11 a/b/g RF transceiver , 0.18um ZigBee CMOS SoC (RF + Baseband + MAC)

Ideally EDA tools are developed with a "push button" goal or "one tool fits all" IC designs. While we all know that is never the case, an IC company needs to allocate resources to architect and develop their own methodologies or flows to fill in the gaps and/or tailor their EDA needs to the type of ICs to be developed. Undertaking this task is very time consuming and adds considerable cost to already very expensive EDA tools. Having the ability to quickly bring in expertise and already architected flows to a particular EDA tool or set of tools will considerably reduce the time and cost by 40% or more. Dice Technology has extensive experience and ready to implement flows in the following areas: place & route, timing analysis, noise analysis (transistor level), repeater insertion, IR drop, EM analysis and more.

Communications standards constraints on jitter are very tight. Placing sensitive analog circuitry, such as a clock generator and/or a clock recovery circuitry, with large digital on the same die requires careful methods to deal with such issues as substrate or interconnect noise. Designing analog circuits that are immune to noise or reduced noise digital libraries also helps. Our mixed-signal methods provide solutions to such issues, therefore reducing the risk of developing faulty products.